Project Status (11/13/2015 - 21:23:07)
Project File: | system.xmp | Implementation State: | Programming File Generated
Module Name: | system | Errors: | No Errors
Product Version: | EDK 14.5 | Warnings: | 73 Warnings (73 new)

XPS Reports | [-]
Report Name | Generated | Errors | Warnings | Infos
Platgen Log File | Fri Nov 13 16:21:44 2015 | 0 | 1 Warning (1 new) | 23 Infos (23 new)
Simgen Log File |  |  |  |
BitInit Log File | Fri Nov 13 16:26:10 2015 | 0 | 0 | 13 Infos (13 new)
System Log File | Fri Nov 13 20:32:37 2015 |  |  |

XPS Synthesis Summary (estimated values) | [-]
Report | Generated | Flip Flops Used | LUTs Used | BRAMS Used | Errors
system | Fri Nov 13 16:22:08 2015 | 2223 | 2270 | 4 | 0
system_proc_sys_reset_0_wrapper | Fri Nov 13 16:21:20 2015 | 69 | 55 |  | 0
system_mdm_0_wrapper | Fri Nov 13 16:21:11 2015 | 123 | 126 |  | 0
system_clock_generator_0_wrapper | Fri Nov 13 16:20:58 2015 |  | 1 |  | 0
system_dip_switches_1_wrapper | Fri Nov 13 16:20:49 2015 | 77 | 43 |  | 0
system_leds_wrapper | Fri Nov 13 16:20:35 2015 | 126 | 64 |  | 0
system_lmb_bram_wrapper | Fri Nov 13 16:20:21 2015 |  |  | 4 | 0
system_ilmb_cntlr_wrapper | Fri Nov 13 16:20:12 2015 | 2 | 6 |  | 0
system_dlmb_cntlr_wrapper | Fri Nov 13 16:20:02 2015 | 2 | 6 |  | 0
system_dlmb_wrapper | Fri Nov 13 16:19:52 2015 | 1 |  |  | 0
system_ilmb_wrapper | Fri Nov 13 16:19:43 2015 | 1 |  |  | 0
system_mb_plb_wrapper | Fri Nov 13 16:19:34 2015 | 155 | 371 |  | 0
system_microblaze_0_wrapper | Fri Nov 13 16:19:20 2015 | 1667 | 1598 |  | 0

Device Utilization Summary (actual values) | [-]
Slice Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Registers | 1,394 | 11,440 | 12% |
Number used as Flip Flops | 1,387 |  |  |
Number used as Latches | 0 |  |  |
Number used as Latch-thrus | 0 |  |  |
Number used as AND/OR logics | 7 |  |  |
Number of Slice LUTs | 1,695 | 5,720 | 29% |
Number used as logic | 1,523 | 5,720 | 26% |
Number using O6 output only | 1,213 |  |  |
Number using O5 output only | 42 |  |  |
Number using O5 and O6 | 268 |  |  |
Number used as ROM | 0 |  |  |
Number used as Memory | 135 | 1,440 | 9% |
Number used as Dual Port RAM | 64 |  |  |
Number using O6 output only | 0 |  |  |
Number using O5 output only | 0 |  |  |
Number using O5 and O6 | 64 |  |  |
Number used as Single Port RAM | 0 |  |  |
Number used as Shift Register | 71 |  |  |
Number using O6 output only | 20 |  |  |
Number using O5 output only | 1 |  |  |
Number using O5 and O6 | 50 |  |  |
Number used exclusively as route-thrus | 37 |  |  |
Number with same-slice register load | 34 |  |  |
Number with same-slice carry load | 3 |  |  |
Number with other load | 0 |  |  |
Number of occupied Slices | 723 | 1,430 | 50% |
Number of MUXCYs used | 204 | 2,860 | 7% |
Number of LUT Flip Flop pairs used | 2,105 |  |  |
Number with an unused Flip Flop | 808 | 2,105 | 38% |
Number with an unused LUT | 410 | 2,105 | 19% |
Number of fully used LUT-FF pairs | 887 | 2,105 | 42% |
Number of unique control sets | 98 |  |  |
Number of slice register sites lost to control set restrictions | 404 | 11,440 | 3% |
Number of bonded IOBs | 11 | 102 | 10% |
Number of LOCed IOBs | 11 | 11 | 100% |
IOB Flip Flops | 8 |  |  |
Number of RAMB16BWERs | 4 | 32 | 12% |
Number of RAMB8BWERs | 0 | 64 | 0% |
Number of BUFIO2/BUFIO2_2CLKs | 1 | 32 | 3% |
Number used as BUFIO2s | 1 |  |  |
Number used as BUFIO2_2CLKs | 0 |  |  |
Number of BUFIO2FB/BUFIO2FB_2CLKs | 0 | 32 | 0% |
Number of BUFG/BUFGMUXs | 2 | 16 | 12% |
Number used as BUFGs | 2 |  |  |
Number used as BUFGMUX | 0 |  |  |
Number of DCM/DCM_CLKGENs | 0 | 4 | 0% |
Number of ILOGIC2/ISERDES2s | 0 | 200 | 0% |
Number of IODELAY2/IODRP2/IODRP2_MCBs | 0 | 200 | 0% |
Number of OLOGIC2/OSERDES2s | 8 | 200 | 4% |
Number used as OLOGIC2s | 8 |  |  |
Number used as OSERDES2s | 0 |  |  |
Number of BSCANs | 1 | 4 | 25% |
Number of BUFHs | 0 | 128 | 0% |
Number of BUFPLLs | 0 | 8 | 0% |
Number of BUFPLL_MCBs | 0 | 4 | 0% |
Number of DSP48A1s | 3 | 16 | 18% |
Number of ICAPs | 0 | 1 | 0% |
Number of MCBs | 0 | 2 | 0% |
Number of PCILOGICSEs | 0 | 2 | 0% |
Number of PLL_ADVs | 1 | 2 | 50% |
Number of PMVs | 0 | 1 | 0% |
Number of STARTUPs | 0 | 1 | 0% |
Number of SUSPEND_SYNCs | 0 | 1 | 0% |
Average Fanout of Non-Clock Nets | 3.82 |  |  |

Performance Summary | [-]
Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | All Constraints Met |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Translation Report | Current | Fri Nov 13 16:23:32 2015 | 0 | 1 Warning (1 new) | 1 Info (1 new)
Map Report | Current | Fri Nov 13 16:24:30 2015 | 0 | 26 Warnings (26 new) | 541 Infos (541 new)
Place and Route Report | Current | Fri Nov 13 16:25:08 2015 | 0 | 20 Warnings (20 new) | 0
Post-PAR Static Timing Report | Current | Fri Nov 13 16:25:19 2015 | 0 | 0 | 3 Infos (3 new)
Bitgen Report | Current | Fri Nov 13 16:25:40 2015 | 0 | 26 Warnings (26 new) | 0

Secondary Reports | [-]
Report Name | Status | Generated
WebTalk Report | Current | Fri Nov 13 16:25:40 2015
WebTalk Log File | Current | Fri Nov 13 16:25:48 2015

Date Generated: 11/13/2015 - 21:23:08